This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to the manufacture and testing of static random access memories (SRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained. However, even when constructed according to complementary metal-oxide-semiconductor (CMOS) technology, SRAM cells conduct some amount of DC current to retain the stored data states.
Designers have recently adopted circuit-based approaches for reducing power consumed by integrated circuits including large memory arrays. One common approach is to reduce the power supply voltage applied to memory arrays, relative to the power supply voltage applied to logic circuitry and circuitry peripheral to the memory array (e.g., decoders, sense amplifiers, etc.). This approach not only reduces the power consumed by the memory array, but also helps to reduce sub-threshold leakage in the individual cells.
Another conventional circuit-based approach to reducing power consumption involves placing the memory functions within the integrated circuit into a “retention” state when possible. In this retention state are, the power supply voltages applied to the memory cells in the array reduced to voltages below that necessary for access, but above the minimum power supply voltage required for each cell to retain its stored data state (i.e., the data-state retention voltage, or “DRV”). Typically, both the “Vdd” power supply voltage applied to the loads of SRAM cells (e.g., the source nodes of the p-channel transistors in CMOS SRAM cells) and also the voltage biasing the transistor body nodes (i.e., the n-well voltage for the p-channel transistors) are reduced in the retention mode. As known in the art, significant recovery time is typically involved in biasing the memory array to an operational state (“wake-up”) from the retention state.
To ensure fidelity of the stored data, conventional SRAM arrays are biased, in the retention state, to a power supply voltage that is above the DRV for the worst memory cell in the array. In many instances, this minimum DRV for the worst cell is identified during manufacturing tests for each integrated circuit, and the retention voltage is “trimmed” (by laser or other programming techniques) to satisfy that worst cell DRV, whether the cell is in the primary array or is a redundant replaced cell. Many modern integrated circuits with significant memory resources sub-divide their memories into multiple “retention domains”, so that those portions of the overall memory space not currently used can be placed into retention. In those architectures, each retention domain can have its own trimmed retention voltage level, to minimize power consumption in retention where possible. However, increasing the granularity of the retention domains to minimize retention power consumption (i.e., by enabling lower retention power supply voltage levels where possible) increases the chip area required for the memory resources, increases test time, complicates the routing of conductors in the integrated circuit realization, and can increase power consumption during operation.
By way of further background, advances in semiconductor technology in recent years have enabled shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. However, this physical scaling of device sizes does not necessarily correlate to similar scaling of device electrical characteristics. In the context of SRAM cells, the memory cell transistors at currently-available minimum feature sizes conduct substantial DC current due to sub-threshold leakage and other short channel effects. As such, the sub-micron devices now used to realize SRAM arrays have increased the DC data retention current drawn by those arrays.
In addition to increasing the data retention current, the continuing scaling down of device sizes has also increased the variability of electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed as variations in the data retention capability of SRAM cells within the same array, such variations being evident on a cell-to-cell basis. At power supply voltages below the DRV for an SRAM cell, one failure mechanism is increased sub-threshold leakage through the off-state driver transistor, which overcomes the drive of the load transistor and thus pulls the stored “1” state past the trip voltage of the cell. The sensitivity of the minimum DRV to device variability is especially high in those memories that are at or near their circuit design limits. And, as mentioned above, sub-threshold leakage is exacerbated in SRAM cells constructed of transistors with sub-micron feature sizes. As such, modern SRAM arrays can have a wide range of DRV performance among their memory cells, with the worst DRV exhibited often being quite poor.
By way of further background, the use of error correction coding (ECC) in connection with solid-state memories is well known. As fundamental in this art, error correction coding involves the storage of additional bits (commonly referred to as parity bits, code bits, checksum digits, ECC bits, etc.) that are determined or calculated from the “payload” data bits being encoded. Typically, the storage of error correction coded data in a memory resource involves the encoding and storing of a code word including both the actual data and also the additional parity bits derived according to the selected ECC code. Retrieval of the stored data involves the decoding of the stored code word according to the same code as used to encode the stored code word. Because the parity bits “over-specify” the actual data portion of the code word, some number of errored bits can be tolerated, without any loss of actual data evident after decoding.
Many ECC coding schemes are well known in the art. Examples of well-known ECC codes include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Typically, the error correction codes used in connection with solid-state memory are “systematic”, in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the parity bits appended to the data bits to form the complete code word. The particular parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. In general, the number of errored bits that can be detected and corrected increases with the number of parity bits generated and stored for a payload data word of a given length.
In many large-scale integrated circuits with embedded memory, error correction is performed on retrieved memory data when those data are communicated over a system bus (i.e., as the data are being communicated from an on-chip memory resource to an on-chip destination, such as an on-chip processor). As known in the art, on-chip ECC exacts a performance penalty due to the time required for ECC of each memory access; additional memory cells must also be provided for storage of the parity bits in those integrated circuits.
The use of error correction to overcome errors in an SRAM caused by reducing the power supply voltage during data retention mode to a level below that of the worst case DRV has been described in Kumar et al., “Fundamental Data Retention Limits in SRAM Standby—Experimental Results”, 9th International Symposium on Quality Electronic Design (IEEE, 2008), pp. 92-97; Qin et al., “Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation”, 9th International Symposium on Quality Electronic Design (IEEE, 2008), pp. 30-34; Kumar et al., “Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM”, International Symposium on Circuits and Systems (IEEE, 2007), pp. 1867-70. These articles describe SRAM architectures in which an ECC encoder and decoder are provided at the input and output, respectively, of the memory array.